The present invention relates to a semiconductor device, and more particularly, to a semiconductor device, which includes a plurality of power transistors, that has a structure enabling miniaturization and improves operational stability.
The size and cost of electronic devices have been reduced. This has resulted in a requirement for miniaturization of power transistors used in such electronic devices. In particular, electronic devices that operate at withstand voltages of 100 V and lower, such as portable devices and household appliances, are required to be further miniaturized. Such electronic devices must employ a technique for integrating a control circuit with a plurality of power transistors on the same semiconductor substrate. A lateral double diffused metal oxide semiconductor field effect transistor (hereafter “LDMOSFET”), which is a known transistor structure that facilitates integration of a plurality of semiconductor elements, is widely used.
An LDMOSFET normally has a drift region formed near its drain to increase the withstand voltage. The drift region is normally requires a length of about 0.067 μm/V. To manufacture, for example, an LDMOSFET having a withstand voltage of 20 V, a drift region having a length of about 1.34μ must be formed by using a submicron fabrication technique. In this manner, the withstand voltage of the LDMOSFET is increased by forming the drift region near the drain. However, the miniaturization of the LDMOSFET is limited by the existence of the drift region.
Japanese Patent No. 3348911 and Japanese Laid-Open Patent Publication No. 2002-184980 describe examples of transistor structures that solve such problems. In the DMOSFET structures described in these documents, a source wire and a drain wire extend from the surface of a semiconductor substrate, and a trench groove is formed in the semiconductor substrate extending in the depthwise direction. A gate electrode is arranged in the trench groove with an insulation film arranged in between. Further, a channel layer and a drift layer are formed in regions of the semiconductor substrate near the side walls of the trench groove. This miniaturizes the DMOS transistor.
The DMOSFET structures described in the above publications reduce the area of the semiconductor substrate occupied by each semiconductor element in comparison with the LDMOSFET structure. Normally, a plurality of power semiconductor elements are connected in parallel to drive a large load. However, reduction in the area occupied by each semiconductor element reduces regions for formation of metal wires that connect semiconductor elements or connect each semiconductor element to an external circuit. This reduces the wiring width of the metal wires and increases the wiring resistance of the metal wires, which lead to the problems described below.
The increased wiring resistance results in application of different voltages to the semiconductor elements although uniform voltage must be applied to the semiconductor elements. This would cause current to concentrate at particular portions of the semiconductor elements. The current concentration may lower the reliability of the semiconductor elements or shorten the lifetime of the wires with respect to fusion and electronic migration. Although the DMOSFET is less likely to have a secondary breakdown than a bipolar transistor, local concentration of current may inflict damages to a DMOSFET.